54ACT11353 Overview
Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe inputs (G) are provided for each of the two four-line sections. With all but one of the mon outputs disabled (at a high-impedance state), the low-impedance of the single enabled output will drive the bus line to a high or low logic level.