Texas Instruments 54F20
The SN54F20 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74F20 is characterized for operation from 0°C to 70°C.| Part No. | 54F20 |
|---|---|
| Datasheet | 54F20 Download |
| Manufacturer |  Texas Instruments |
| Description | DUAL 4-INPUT POSITIVE-NAND GATES |
| Buy | Stock & Price |
SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES
● Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent 4-input NAND gates. They perform the Boolean functions Y = A
● B
● C
● D or Y = A + B + C + D in positive logic. SDFS041A – MARCH 1987 – REVISED OCTOBER 1993 SN54F20 . . . J PACKAGE SN74F20 . . . D OR N PACKAGE (TOP VIEW) 1A 1 1B 2 NC 3 1C 4 1D 5 1Y 6 GND 7 14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y SN54F20 . . . FK PACKAGE (TOP VIEW) 2D VCC NC 1A 1B FUNCTION TABLE (each gate) INPUTS OUTPUT A B C D Y H H H H L L X X X H X L X X H X X L X H X X X L H logic symbol† 1 1A & 2 1B 4 1C 5 1D 9 2A 10 2B 12 2C 13 2D NC 3 2 1 20 19 4 18 2C NC 5 17 NC 1C 6 16 NC NC 7 15 NC 1D 8 14 2B 9 10 11 12 13 2A 2Y NC GND 1Y NC – No internal connection 6 1Y 8 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram, each gate (positive logic) A B Y C D PRODUCTION DATA information is current as of publication date.
● Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent 4-input NAND gates. They perform the Boolean functions Y = A
● B
● C
● D or Y = A + B + C + D in positive logic. SDFS041A – MARCH 1987 – REVISED OCTOBER 1993 SN54F20 . . . J PACKAGE SN74F20 . . . D OR N PACKAGE (TOP VIEW) 1A 1 1B 2 NC 3 1C 4 1D 5 1Y 6 GND 7 14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y SN54F20 . . . FK PACKAGE (TOP VIEW) 2D VCC NC 1A 1B FUNCTION TABLE (each gate) INPUTS OUTPUT A B C D Y H H H H L L X X X H X L X X H X X L X H X X X L H logic symbol† 1 1A & 2 1B 4 1C 5 1D 9 2A 10 2B 12 2C 13 2D NC 3 2 1 20 19 4 18 2C NC 5 17 NC 1C 6 16 NC NC 7 15 NC 1D 8 14 2B 9 10 11 12 13 2A 2Y NC GND 1Y NC – No internal connection 6 1Y 8 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram, each gate (positive logic) A B Y C D PRODUCTION DATA information is current as of publication date.
