Texas Instruments 54F374
The eight flip-flops of the ′F374 are edge-triggered D-type flip-flops. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.| Part No. | 54F374 |
|---|---|
| Datasheet | 54F374 Download |
| Manufacturer |  Texas Instruments |
| Description | Octal Edge-Triggered D-Type Flip-Flops |
| Buy | Stock & Price |
SN54F374, SN74F374 OCTAL EDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH 3ĆSTATE OUTPUTS SDFS077A − D2932, MARCH 1987 − REVISED OCTOBER 1993
● Eight D-Type Flip-Flops in a Single Package
● 3-State Bus-Driving True Outputs
● Full Parallel Access for Loading
● Buffered Control Inputs
● Package Options Include Plastic Small-Outline (SOIC) and Shrink Small-Outline (SSOP) Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs description These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54F374 . . . J PACKAGE SN74F374 . . . DB, DW, OR N PACKAGE (TOP VIEW) OE 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK SN54F374 . . . FK PACKAGE (TOP VIEW) 8Q VCC OE 1Q 1D On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
● Eight D-Type Flip-Flops in a Single Package
● 3-State Bus-Driving True Outputs
● Full Parallel Access for Loading
● Buffered Control Inputs
● Package Options Include Plastic Small-Outline (SOIC) and Shrink Small-Outline (SSOP) Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs description These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54F374 . . . J PACKAGE SN74F374 . . . DB, DW, OR N PACKAGE (TOP VIEW) OE 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK SN54F374 . . . FK PACKAGE (TOP VIEW) 8Q VCC OE 1Q 1D On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
