Datasheet Summary
74AC11004 HEX INVERTER
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
D EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-μm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)
SCAS033B
- JANUARY 1988
- REVISED APRIL 1996
DB, DW, OR N PACKAGE (TOP VIEW)
1Y 2Y 3Y GND GND GND GND 4Y 5Y 6Y
1 2 3 4 5 6 7 8 9 10
20 1A 19 2A 18 3A 17 NC 16 VCC 15 VCC 14 NC 13 4A 12 5A 11 6A description
- No internal connection
This device contains six independent inverters. It performs the Boolean...