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74AC11013 DUAL 4-INPUT POSITIVE-NAND SCHMITT TRIGGER
• Operation From Very Slow Edges • Improved Line-Receiving Characteristics • High Noise Immunity • Flow-Through Architecture Optimizes PCB
Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at
125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
SCAS112 – MARCH 1990 – REVISED APRIL 1993
D OR N PACKAGE (TOP VIEW)
1B 1A 1Y GND 2Y 2D 2C
1 2 3 4 5 6 7
14 NC 13 1C 12 1D 11 VCC 10 2A 9 2B 8 NC
description
Each circuit functions as a 4-input NAND gate, but because of the Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (
74AC11013 Datasheet
