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74AC11138 - 3-Line To 8-Line Decoder/Demultiplexer

General Description

The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.

In high-performance memory systems, this decoder can be used to minimize the effects of system decoding.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AC11138 3ĆLINE TO 8ĆLINE DECODER/DEMULTIPLEXER D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) SCAS042B − MAY 1988 − REVISED APRIL 1996 D, N, OR PW PACKAGE (TOP VIEW) Y1 Y2 Y3 GND Y4 Y5 Y6 Y7 1 2 3 4 5 6 7 8 16 Y0 15 A 14 B 13 C 12 VCC 11 G1 10 G2A 9 G2B description The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routin