Texas Instruments 74AC11239
The 74AC11239 circuit is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.| Part No. | 74AC11239 |
|---|---|
| Datasheet | 74AC11239 Download |
| Manufacturer |  Texas Instruments |
| Description | DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER |
| Buy | Stock & Price |
74AC11239 DUAL 2–LINE TO 4–LINE DECODER/DEMULTIPLEXER
● Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
● Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t● EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs SCAS072A – JULY 1989 – REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) 1Y1 1Y2 1Y3 GND 2Y0 2Y1 2Y2 2Y3 1 2 3 4 5 6 7 8 16 1Y0 15 1A 14 1B 13 1G 12 VCC 11 2G 10 2A 9 2B description In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. The 74AC11239 is comprised of two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications.
● Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
● Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t● EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs SCAS072A – JULY 1989 – REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) 1Y1 1Y2 1Y3 GND 2Y0 2Y1 2Y2 2Y3 1 2 3 4 5 6 7 8 16 1Y0 15 1A 14 1B 13 1G 12 VCC 11 2G 10 2A 9 2B description In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. The 74AC11239 is comprised of two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications.
