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74AC11239 - DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

General Description

The 74AC11239 circuit is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times.

In high-performance memory systems, this decoder can be used to minimize the effects of system decoding.

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Other Datasheets by Texas Instruments

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AC11239 DUAL 2–LINE TO 4–LINE DECODER/DEMULTIPLEXER • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems • Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception • Flow-Through Architecture to Optimize PCB Layout • Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t• EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs SCAS072A – JULY 1989 – REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) 1Y1 1Y2 1Y3 GND 2Y0 2Y1 2Y2 2Y3 1 2 3 4 5 6 7 8 16 1Y0 15 1A 14 1B 13 1G 12 VCC 11 2G 10 2A 9 2B description The 74AC11239 circuit is designed to be used in high-performance memory-deco