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74AC11273 - OCTAL D-TYPE FLIP-FLOP

General Description

These positive-edge-triggered flip-flops implement D-type flip-flop logic with a direct clear input.

Data at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

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Full PDF Text Transcription for 74AC11273 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AC11273. For precise diagrams, and layout, please refer to the original PDF.

• Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators • Flow-Through Architecture to Optimize PCB Layout • Multiple Center-Pin VCC and GND C...

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rchitecture to Optimize PCB Layout • Multiple Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t• EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs 74AC11273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SCAS497 – D3442, MARCH 1990 – REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 CLR 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 CLK description These positive-edge-triggered flip-fl

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