Datasheet Summary
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- Inputs Are TTL-Voltage patible
- Flow-Through Architecture to Optimize
PCB Layout
- Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
- EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic
Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description
These devices contain three independent 3-input NAND gates. They perform the Boolean functions Y = ASBSC or Y = A + B + C in positive logic.
The 54ACT11010 is characterized for operation over the full military temperature range of
- 55°C to 125°C. The 74ACT11010 is characterized for...