Datasheet Summary
74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES
D Inputs Are TTL-Voltage patible D Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic
Small-Outline Packages (D), Plastic Shrink
Small-Outline Packages (DB), Plastic Thin
Shrink Small-Outline Packages (PW), and
Standard Plastic 300-mil DIPs (N)
SCAS008C
- JULY 1987
- REVISED APRIL 1996
D, DB, N, OR PW PACKAGE (TOP VIEW)
1A 1 1Y 2 2Y 3 GND 4 GND 5 3Y 6 4Y 7
4B 8
16 1B 15 2A 14 2B 13 VCC 12 VCC 11 3A
10 3B
9 4A description
This device contains four independent 2-input OR gates....