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74ACT11112 Datasheet Dual J-k Negative-edge-triggered Flip-flop

Manufacturer: Texas Instruments

Overview: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • Inputs Are TTL-Voltage Compatible • Fully Buffered to Offer Maximum Isolation From External.

General Description

This device contains two independent J-K negative-edge-triggered flip-flops.

A low level at the PRE or CLR input sets or resets the outputs regardless of the levels of the other inputs.

When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse.

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