Datasheet Summary
74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCAS064A
- D3339, JUNE 1989
- REVISED APRIL 1993
- Inputs Are TTL-Voltage patible
- Fully Buffered to Offer Maximum Isolation
From External Disturbance
- Flow-Through Architecture Optimizes
PCB Layout
- Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise t- EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
D OR N PACKAGE (TOP VIEW)
1PRE 1Q 1Q
GND 2Q 2Q
2PRE 2J
1 2 3 4 5 6 7 8
16 1J 15 1K 14 1CLK 13 1CLR 12 VCC 11 2CLR 10 2CLK 9 2K description
This...