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• Inputs Are TTL-Voltage Compatible • Center-Pin VCC and GND Pin Configurations
Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic
Small-Outline Packages and Standard Plastic 300-mil DIPs
description
74ACT11132 QUADRUPLE POSITIVEĆNAND GATE
WITH SCHMITTĆTRIGGER INPUTS
SCAS177 − D3974, JANUARY 1992 − REVISED APRIL 1993
D OR N PACKAGE (TOP VIEW)
1A 1Y 2Y GND GND 3Y 4Y 4B
1 2 3 4 5 6 7 8
16 1B 15 2A 14 2B 13 VCC 12 VCC 11 3A
10 3B
9 4A
This device contains four independent 2-input NAND gates with Schmitt-trigger inputs. Because of the Schmitt action, they have different input threshold levels for positive- and negative-going signals.
74ACT11132 Datasheet
