Texas Instruments 74ACT11534
The 74ACT11534 is characterized for operation from − 40°C to 85°C.ą 54ACT11534, 74ACT11534 OCTAL DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS WITH 3ĆSTATE OUTPUTS SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
● Eight D-Type Flip-Flops in a Single Package
● 3-State Bus Driving Inverting Outputs
● Full Parallel Access for Loading
● Inputs Are TTL-Voltage Compatible
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
● EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description 54ACT11534 . . . JT PACKAGE 74ACT11534 . . . DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 OC 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 CLK 54ACT11534 . . . FK PACKAGE (TOP VIEW) 3D 4D VCC NC VCC 5D 6D These eight flip-flops feature 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
● Eight D-Type Flip-Flops in a Single Package
● 3-State Bus Driving Inverting Outputs
● Full Parallel Access for Loading
● Inputs Are TTL-Voltage Compatible
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
● EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description 54ACT11534 . . . JT PACKAGE 74ACT11534 . . . DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 OC 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 CLK 54ACT11534 . . . FK PACKAGE (TOP VIEW) 3D 4D VCC NC VCC 5D 6D These eight flip-flops feature 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.