Texas Instruments 74ACT11657
The 74ACT11657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker and is intended for busoriented applications. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.| Part No. | 74ACT11657 |
|---|---|
| Datasheet | 74ACT11657 Download |
| Manufacturer |  Texas Instruments |
| Description | OCTAL TRANSCEIVER |
| Buy | Stock & Price |
74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCAS232 – AUGUST 1992 – REVISED APRIL 1993
● Inputs Are TTL-Voltage Compatible
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise
● EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description DW PACKAGE (TOP VIEW) PARITY A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 ERR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 OE 27 B1 26 B2 25 B3 24 B4 23 VCC 22 VCC 21 VCC 20 B5 19 B6 18 B7 17 B8 16 ODD/EVEN 15 T/R The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceivers. Odd or even parity is selected by a logic high or low level, respectively, on the ODD/EVEN input. PARITY carries the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.
● Inputs Are TTL-Voltage Compatible
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise
● EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description DW PACKAGE (TOP VIEW) PARITY A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 ERR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 OE 27 B1 26 B2 25 B3 24 B4 23 VCC 22 VCC 21 VCC 20 B5 19 B6 18 B7 17 B8 16 ODD/EVEN 15 T/R The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceivers. Odd or even parity is selected by a logic high or low level, respectively, on the ODD/EVEN input. PARITY carries the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.
