74ACT11898 Datasheet | Texas Instruments

description The 74ACT11898 features AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit plete control over ining data. A low at either input inhibits entry of new data and resets the first flip-flop to the low level on the rising edge of the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low provided the minimum setup and hold time requirements are met. Clocking occurs on the low-to-high transition of the clock input. The 74ACT11898 is characterized for operation from - 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS CLR CLK LX B QA QB ... QJ H L X X QA0 QB0 H ↑ H H H QAN H ↑ L X L QAN H ↑ X L L QAN H = high level (steady state) X = irrelevant (any input, including transitions) ↑ = transition from low to high level QA0, QB0, QJ0 = the level of QA, QB, QJ respectively, before the indicated steady-state inputconditions were established. Qn, Qin = the level or QA or QJ before the most recent ↑ transition of the clock; indicates aone-bit shift.t EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 2- 1 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCAS144 - OCTOBER 1990 - REVISED APRIL 1993 logic symbol† logic diagram (positive logic) CLK CLR 13 18 SRG10 C1/ 17 A 14 B &...