74LV244AT Overview
/ORDERING INFORMATION This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs.
74LV244AT Key Features
- Inputs Are TTL-Voltage patible
- 4.5-V to 5.5-V VCC Operation
- Typical tpd = 5.4 ns at 5 V
- Typical VOLP (Output Ground Bounce)
- Typical VOHV (Output VOH Undershoot)
- Supports Mixed-Mode Voltage Operation on
- JUNE 2004
- REVISED AUGUST 2005
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
