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ADC08D1520QML-SP - 8-Bit A/D Converter

General Description

The ADC08D1520 is an 8

Bit, dual channel, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1000 platform.

The ADC08D1520 digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS.

Key Features

  • 1.
  • 2 Total Ionizing Dose 300 krad(Si).
  • Single Event Latch-up 120 MeV-cm2/mg.
  • Single +1.9V ±0.1V Operation.
  • Interleave Mode for 2x Sample Rate.
  • Multiple ADC Synchronization Capability.
  • Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment.
  • Choice of SDR or DDR output clocking.
  • 1:1 or 1:2 Selectable Output Demux.
  • Second DCLK output.
  • Duty Cycle Corrected Sample Clock.
  • Test pattern.

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📁 Similar Datasheet

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ADC08D1520 Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter National Semiconductor
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Other Datasheets by Texas Instruments

Part Number Description
ADC08D1520 8-Bit A/D Converter
ADC08D1500 Dual 8-Bit A/D Converter
ADC08D1000 Dual 8-Bit A/D Converter
ADC08D1000QML 1 GSPS A/D Converter
ADC08D1000QML-SP 1 GSPS A/D Converter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ADC08D1520QML-SP www.ti.com SNAS420O – JANUARY 2008 – REVISED MARCH 2013 ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter FEATURES 1 •2 Total Ionizing Dose 300 krad(Si) • Single Event Latch-up 120 MeV-cm2/mg • Single +1.9V ±0.1V Operation • Interleave Mode for 2x Sample Rate • Multiple ADC Synchronization Capability • Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment • Choice of SDR or DDR output clocking • 1:1 or 1:2 Selectable Output Demux • Second DCLK output • Duty Cycle Corrected Sample Clock • Test pattern • Serial Interface for Extended Control KEY SPECIFICATIONS • Resolution 8 Bits • Max Conversion Rate 1.5 GSPS (min) • Code Error Rate 10-18 (typ) • ENOB at 748 MHz Input 7.2 Bits (typ) • DNL ±0.