ADC12D040 Datasheet | Texas Instruments

FEATURES - 2 Binary or 2’s plement Output Format - Single Supply Operation - Internal Sample-and-Hold - Outputs 2.4V to 5V patible - Power Down Mode - Pin-patible with ADC12DL066 - Internal/External Reference APPLICATIONS - Ultrasound and Imaging - Instrumentation - munications Receivers - Sonar/Radar - x DSL - Cable Modems KEY SPECIFICATIONS - SNR (f IN = 10 MHz): 68 d B (typ) - ENOB (f IN = 10 MHz): 10.9 bits (typ) - SFDR (f IN = 10 MHz): 80 d B (typ) - Data Latency: 6 Clock Cycles - Supply Voltage: +5V ±5% - Power Consumption, Operating - (Operating): 600 m W (typ) - (Power Down Mode): 75 m W (typ) DESCRIPTION The ADC12D040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (Msps), minimum. This converter uses a differential, pipeline architecture with digital error correction and an onchip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, the ADC12D040 achieves 10.9 effective bits at 10 MHz input and consumes just 600 m W at 40 Msps, including the reference current. The Power Down feature reduces power consumption to 75 m W. The differential inputs provide a full scale differential input swing equal to 2VREF with the possibility of a single-ended input. Full use of the differential input is remended for optimum performance. The digital outputs for the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or 2’s plement. For ease of interface, the digital output driver power pins of the ADC12D040 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage, making the outputs patible with low voltage systems. The ADC12D040’s speed, resolution and single supply operation make it well suited for a variety of applications. This device is available in the 64-lead TQFP package and...