ADC14DS080 Datasheet | Texas Instruments

.ti. SNAS428B - SEPTEMBER 2007 - REVISED APRIL 2013 ADC14DS080 Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs Check for Samples: ADC14DS080 Features - 2 Clock Duty Cycle Stabilizer - Single +3.0V or 3.3V Supply Operation - Serial LVDS Outputs - Serial Control Interface - Overrange Outputs - 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch) APPLICATIONS - High IF Sampling Receivers - Wireless Base Station Receivers - Test and Measurement Equipment - munications Instrumentation - Portable Instrumentation KEY SPECIFICATIONS - Resolution: 14 Bits - Conversion Rate: 80 MSPS - SNR: (f IN = 170 MHz) 72 d BFS (typ) - SFDR: (f IN = 170 MHz) 82 d BFS (typ) - Full Power Bandwidth: 1 GHz (typ) - Power Consumption: 800 m W (typ) DESCRIPTION The ADC14DS080 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 14-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external ponent count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14DS080 may be operated from a single +3.0V or 3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14DS080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's plement) and duty cycle stabilizer are selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. A serial interface allows access to the control registers...