AM5K2E04
Features and Description
1.1 Features
- ARM® Cortex®-A15 MPCore™ Core Pac
- Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz
- 4MB L2 Cache Memory Shared by all Cortex A15 Processor Cores
- Full Implementation of ARMv7-A Architecture Instruction Set
- 32KB L1 Instruction and Data Caches per Core
- AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3
- Multicore Shared Memory Controller (MSMC)
- 2 MB SRAM Memory for ARM Core Pac
- Memory Protection Unit for Both SRAM and DDR3_EMIF
- Multicore Navigator
- 8k Multi-Purpose Hardware Queues with Queue Manager
- One Packet-Based DMA Engine for Zero Overhead Transfers
- Network Coprocessor
- Packet Accelerator Enables Support for
- Transport Plane IPsec, GTP-U, SCTP, PDCP
- L2 User Plane PDCP (Ro HC, Air Ciphering)
- 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second
- Security Accelerator Engine Enables Support for
- IPSec, SRTP, 3GPP...
