CD54HC175
Features
- mon Clock and Asynchronous Reset on Four D-Type Flip-Flops
- Positive Edge Pulse Triggering
- plementary Outputs
- Buffered Inputs
- Fanout (Over Temperature Range)
- Standard Outputs
- -
- 10 LSTTL Loads
- Bus Driver Outputs
- - . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55o C to 125o C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction pared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input patibility, Il ≤ 1µA at VOL, VOH
Description advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.
Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a mon clock (CP) and a mon reset (MR). Resetting is...
