Texas Instruments CD54HC259
The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky. This latches three active modes and one reset mode.| Part No. | CD54HC259 |
|---|---|
| Datasheet | CD54HC259 Download |
| Manufacturer |  Texas Instruments |
| Description | 8-Bit Addressable Latch |
| Buy | Stock & Price |
FEATURES
DESCRIPTION
● Buffered Inputs and Outputs● Four Operating Modes
● Typical Propagation Delay CL = 15pF, TA = 25oC of 15ns at VCC = 5V,
● Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
● Wide Operating Temperature Range . . . -55oC to 125oC
● Balanced Propagation Delay and Transition Times
● Significant Power Reduction Compared to LSTTL Logic ICs
● HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
● HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE transition from low to high.
