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Data sheet acquired from Harris Semiconductor SCHS135F
March 1998 - Revised October 2003
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75
Dual 2-Bit Bistable Transparent Latch
[ /Title (CD74 HC75, CD74 HCT75 ) /Subject (Dual 2-Bit Bistabl e
Features
Description
• True and Complementary Outputs
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output.