CD54HCT563 Datasheet | Texas Instruments

Data sheet acquired from Harris Semiconductor SCHS187C January 1998 - Revised July 2003 CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs [ /Title (CD74H C533, CD74H CT533, CD74H C563, CD74H CT563) /Subject (High Speed Features Description - mon Latch-Enable Control - mon Three-State Output Enable Control - Buffered Inputs - Three-State Outputs - Bus Line Driving Capacity - TCy Lp=ic1a5l p PFr,o Tp Aag=a2ti5oon CD(e Dlaatya=to13Onustpaut t V) CC = 5V, - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL,...