Datasheet4U Logo Datasheet4U.com

CD74ACT109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

Datasheet Summary

Description

The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

📥 Download Datasheet

Datasheet preview – CD74ACT109

Datasheet Details

Part number CD74ACT109
Manufacturer Texas Instruments
File Size 475.21 KB
Description DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
Datasheet download datasheet CD74ACT109 Datasheet
Additional preview pages of the CD74ACT109 datasheet.

📁 Similar Datasheet

  • CD7401 - Speaker (Turbosonic)
  • CD746A - ZENER DIODE (Compensated Deuices)
  • CD746A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD747A - ZENER DIODE (Compensated Deuices)
  • CD747A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD748A - ZENER DIODE (Compensated Deuices)
  • CD748A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD749A - ZENER DIODE (Compensated Deuices)
  • CD749A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD74FCT2245T - Fast CMOS Octal Bidirectional Transceivers (Harris Semiconductor)
Other Datasheets by Texas Instruments
  • CD74ACT10 - TRIPLE 3-INPUT POSITIVE-NAND GATES
  • CD74ACT112 - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
  • CD74ACT138 - 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
  • CD74ACT139 - DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
  • CD74ACT14 - Hex Schmitt-Trigger Inverter
  • CD74ACT151 - 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
  • CD74ACT153 - DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
  • CD74ACT157 - QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

Full PDF Text Transcription

Click to expand full text
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT109 . . . F PACKAGE CD74ACT109 . . . E OR M PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q description/ordering information The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops.
Published: |