CD74HC243 Datasheet | Texas Instruments

Data sheet acquired from Harris Semiconductor SCHS168D November 1997 - Revised October 2003 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs [ /Title (CD74 HCT24 2, CD74 HC243 , CD74 HCT24 3) /Subject (High Speed CMOS Logic Quad- Features Description - Typical Propagation Delay (A to B, B to A) of 7ns at VCC = 5V, CL = 15p F, TA = 25o C - Three-State Outputs - Buffered Inputs - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH The ’HC243 and ’HCT243 silicon-gate CMOS three-state bidirectional noninverting buffers are intended for two-way asynchronous munication between data buses. They have high-drive-current outputs that enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits and have speeds parable to low-power Schottky TTL circuits. They can drive 15 LSTTL loads. The states of the output-enable (OEB, OEA) inputs determine both the direction of flow (A to B, B to A), and the three-state...