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CD74HC297 - Digital Phase-Locked Loop

General Description

Digital Design Avoids Analog Compensation Errors Easily Cascadable for Higher Order Loops Useful Frequency Range - K-Clock .DC to 55MHz (Typ) - I/D-Clock DC to 35MHz (Typ) Dynami

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Full PDF Text Transcription (Reference)

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Data sheet acquired from Harris Semiconductor SCHS177B November 1997 - Revised May 2003 CD54HC297, CD74HC297, CD74HCT297 High-Speed CMOS Logic Digital Phase-Locked Loop [ /Title (CD74 HC297 , CD74 HCT29 7) /Subject (HighSpeed CMOS Logic Digital PhaseLocked Features Description • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically Variable Bandwidth • Very Narrow Bandwidth Attainable • Power-On Reset • Output Capability - Standard . . . . . . . . . . . . . . . . . . . . XORPDOUT, ECPDOUT - Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .