CD74HC4040M Datasheet | Texas Instruments

Data sheet acquired from Harris Semiconductor SCHS203D February 1998 - Revised October 2003 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter [ /Title (CD74H C4040, CD74HC T4040) /Subject (High Speed CMOS Logic 12-Stage Binary Features Description - Fully Static Operation - Buffered Inputs - mon Reset - Negative Edge Pulsing - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH The ’HC4040 and ’HCT4040 are 14-stage ripple-carry binary counters. All counter stages are master-slave flipflops. The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. Ordering...