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CD74HCT137 - High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer

Download the CD74HCT137 datasheet PDF. This datasheet also includes the CD74HC137 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CD74HC137-etcTI.pdf) that lists specifications for multiple related part numbers.

General Description

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes.

A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder.

Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and to facilitate demultiplexing.

Overview

Data sheet acquired from Harris Semiconductor SCHS146F March 1998 - Revised October 2003 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address.

Key Features

  • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237.
  • l/O Port or Memory Selector.
  • Two Enable Inputs to Simplify Cascading.
  • Typical Propagation Delay of 13ns 15pF, TA = 25oC (CD74HC237) at VCC = 5V,.
  • Fanout (Over Temperature Range) - Standard Outputs.
  • 10 LSTTL Loads - Bus Driver Outputs.
  • . . . 15 LSTTL Loads.
  • Wide Operating T.