CDCLVP110 Overview
The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under...
CDCLVP110 Key Features
- Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
- Fully patible With LVECL/LVPECL/HSTL
- Single Supply Voltage Required, ±3.3-V or
- Selectable Clock Input Through CLK_SEL
CDCLVP110 Applications
- VBB Reference Voltage Output for