CDCM1804 Overview
The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50-Ω transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3.
CDCM1804 Key Features
- Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
- Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
- Low-Output Skew 15 ps (Typical) for Clock-Distribution