Datasheet Details
| Part number | CDCVF111 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 513.72 KB |
| Description | 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER |
| Datasheet |
 CDCVF111 Datasheet
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| Part number | CDCVF111 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 513.72 KB |
| Description | 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER |
| Datasheet |
CDCVF111 Datasheet
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The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution.
It is specifically designed for driving 50-Ω transmission lines.
FN PACKAGE (TOP VIEW) NC VREF CLKIN VCC CLKIN NC GND Y8 Y8 Y7 VCC Y7 Y6 Y6 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y0 Y0 Y1 VCC Y1 Y2 Y2 Y5 Y5 Y4 VCC Y4 Y3 Y3 NC – No internal connection The VREF output can be strapped to the CLKIN input for a single-ended CLKIN input.
CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution Applications D Differential Low-Voltage Pseudo-ECL (LVPECL) Compatible Inputs and.
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|---|---|
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| CDCVF2509A | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| CDCVF2510 | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| CDCVF2510A | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |