CDCVF855 Overview
The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 4 differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high,...
CDCVF855 Key Features
- Spread-Spectrum Clock patible
- Operating Frequency: 60 MHz to 220 MHz
- Low Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200
- Low Static Phase Offset: ±50 ps
- Low Jitter (Period): ±60 ps (±30 ps at 200 MHz)
- 1-to-4 Differential Clock Distribution (SSTL2)
- Best in Class for VOX = VDD/2 ±0.1 V
- Operates From Dual 2.6-V or 2.5-V Supplies
- Available in a 28-Pin TSSOP Package
- Consumes < 100-µA Quiescent Current