CY54FCT377T Datasheet | Texas Instruments

description The ’FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The mon buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE must be stable only one setup time prior to the low-to-high clock transition for predictable operation. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2001, Texas Instruments Incorporated On products pliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. CY54FCT377T, CY74FCT377T 8-BIT REGISTERS SCCS023A - MAY 1994 - REVISED OCTOBER 2001 ORDERING INFORMATION PACKAGE† SPEED (ns) ORDERABLE PART NUMBER TOP-SIDE MARKING QSOP - Q Tape and reel 5.2 CY74FCT377CTQCT FCT377C Tube SOIC - SO Tape and reel 5.2 CY74FCT377CTSOC FCT377C 5.2 CY74FCT377CTSOCT - 40°C to 85°C QSOP - Q Tape and reel 7.2 CY74FCT377ATQCT FCT377A Tube SOIC -...