CY74FCT2373T Datasheet | Texas Instruments

D Function and Pinout patible With the Fastest Bipolar Logic D 25-Ω Output Series Resistors Reduce Transmission-Line Reflection Noise D Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D 3-State Outputs D ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) D Fully patible With TTL Input and Output Logic Levels D 12-m A Output Sink Current 15-m A Output Source Current CY74FCT2373T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS039B - SEPTEMBER 1994 - REVISED OCTOBER 2001 Q OR SO PACKAGE (TOP VIEW) O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 O7 18 D7 17 D6 16 O6 15 O5 14 D5 13 D4 12 O4 11 LE description The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-patible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-Ω termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the CY74FCT373T to reduce noise in an existing design. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered into the...