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DAC5674
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
14ĆBIT, 400 MSPS, 2y/4y INTERPOLATING CommsDAC DIGITALĆTOĆANALOG CONVERTER
FEATURES
D 200-MSPS Maximum Input Data Rate
D 400-MSPS Maximum Update Rate DAC
D 76-dBc SFDR Over Full First Nyquist Zone
With Single Tone Input Signal (Fout = 21 MHz)
D 74-dBc ACPR W-CDMA at 15.36 MHz IF
D 69-dBc ACPR W-CDMA at 30.72 MHz IF
D Selectable 2y or 4y Interpolation Filter
− Linear Phase − 0.05-dB Pass-Band Ripple − 80-dB Stop-Band Attenuation − Stop-Band Transition 0.4−0.6 Fdata − Interpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For Selection High-Order Images
D On-Chip 2y/4y PLL Clock Multiplier, PLL
Bypass Mode
D Differential Scalable Current Outputs: 2 mA to
20 mA
D On-Chip 1.2-V Reference D 1.
DAC5674 Datasheet
