DAC5674
FEATURES
D 200-MSPS Maximum Input Data Rate
D 400-MSPS Maximum Update Rate DAC
D 76-d Bc SFDR Over Full First Nyquist Zone
With Single Tone Input Signal (Fout = 21 MHz)
D 74-d Bc ACPR W-CDMA at 15.36 MHz IF
D 69-d Bc ACPR W-CDMA at 30.72 MHz IF
D Selectable 2y or 4y Interpolation Filter
- Linear Phase
- 0.05-d B Pass-Band Ripple
- 80-d B Stop-Band Attenuation
- Stop-Band Transition 0.4- 0.6 Fdata
- Interpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For Selection High-Order Images
D On-Chip 2y/4y PLL Clock Multiplier, PLL
Bypass Mode
D Differential Scalable Current Outputs: 2 m A to
20 m A
D On-Chip 1.2-V Reference D 1.8-V Digital and 3.3-V Analog Supply
Operation
D 1.8/3.3-V CMOS patible Interface D Power Dissipation: 435 m W at 400 MSPS D Package: 48-Pin TQFP
APPLICATIONS
D Cellular Base Transceiver Station Transmit
Channel
- CDMA: W-CDMA, CDMA2000, IS-95
- TDMA: GSM, IS-136, EDGE/UWC-136
D Test and Measurement: Arbitrary Waveform
Generation
D Direct Digital...
