DS36950 Datasheet | Texas Instruments

FEATURES - 2 Pinout for IPI Interface - pact 20-pin PLCC Package - Meets EIA-485 Standard for Multipoint Bus Transmission - Greater than 60 m A Source/Sink - Thermal Shutdown Protection DESCRIPTION The DS36950 is a low power, space-saving quad EIA-485 differential bus transceiver especially suited for high speed, parallel, multipoint, puter I/O bus applications. A pact 20-pin surface mount PLCC package provides high transceiver integration and a very small PC board footprint. Timing uncertainty across an interface using multiple devices, a typical problem in a parallel interface, is specified- minimum and maximum propagation delay times are guaranteed. Six devices can implement a plete IPI master or slave interface. Three transceivers in a package are pinned out for connection to a parallel databus. The fourth transceiver, with the flexibility provided by its individual enables, can serve as a control bus transceiver. Pinout and Logic Diagram Figure 1. Top View (Package Number FN0020A) Figure 2. Block Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998- 2013, Texas Instruments Incorporated SNLS075C - JULY 1998 - REVISED FEBRUARY 2013 .ti. Absolute Maximum Ratings (1)(2) Supply Voltage Control Input Voltage Driver Input Voltage Driver Output Voltage/Receiver Inpu...