DS90CR485 Overview
The DS90CR485 device serializes the 24 LVCMOS/LVTTL double-edge inputs (48 bits data latched in per clock cycle) onto eight Low Voltage Differential Signaling (LVDS) streams. A phaselocked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost.
DS90CR485 Key Features
- 1 Up to 6.384-Gbps Throughput
- 66-MHz to 133-MHz Input Clock Support
- Reduces Cable and Connector Size and Cost
- Pre-Emphasis Reduces Cable Loading Effects
- DC Balance Reduces ISI Distortion
- 24-Bit Double Edge Inputs
- 3-V Tolerant LVCMOS/LVTTL Inputs
- Low Power, 2.5-V Supply
- Flow-Through Pinout
- 100-Pin TQFP Package
