DS90LV004 Datasheet | Texas Instruments

FEATURES - 23 1.5 Gbps data rate per channel - Configurable pre-emphasis drives lossy backplanes and cables - Low output skew and jitter - LVDS/CML/LVPECL patible input, LVDS output - On-chip 100Ω input and output termination - 12 k V ESD protection on LVDS outputs - Single 3.3V supply - Very low power consumption - Industrial -40 to +85°C temperature range - Small TQFP Package Footprint - Evaluation Kit Available - See SCAN90004 for JTAG-enabled version DESCRIPTION The DS90LV004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flowthrough pinout minimize internal device jitter and simplify board layout, while configurable preemphasis overes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS Ser Des, as well as CML and LVPECL. The differential inputs and outputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes. Typical Application Cable or Backplane FPGA or ASIC LVDS I/O FPGA or ASIC LVDS I/O Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TRI-STATE is a registered trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005- 2013, Texas Instruments Incorporated SNLS190P - APRIL 2005 - REVISED APRIL 2013 Block and Connection Diagrams PEM0...