HC165Q1 Datasheet | Texas Instruments

SN74HC165ĆQ1 8ĆBIT PARALLELĆLOAD SHIFT REGISTER D Qualified for Automotive Applications D ESD Protection Exceeds 1500 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 13 ns D ±4-m A Output Drive at 5 V D Low Input Current of 1 µA Max D plementary Outputs D Direct Overriding Load (Data) Inputs D Gated Clock Inputs D Parallel-to-Serial Data Conversion SCLS518A - AUGUST 2003 - REVISED APRIL 2008 D OR PW PACKAGE (TOP VIEW) SH/LD 1 CLK 2 E3 F4 G5 H6 QH 7 GND 8 16 VCC 15 CLK INH 14 D 13 C 12 B 11 A 10 SER 9 QH description/ordering information The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A- H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 also Features a clock-inhibit (CLK INH) function and a plementary serial (QH) output. Clocking is acplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also acplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. ORDERING INFORMATION{ PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC - D - 40°C to 125°C TSSOP - PW Tape and reel Tape and reel SN74HC165QDRQ1 SN74HC165QPWRQ1 HC165Q1 HC165Q1 † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://.ti.. ‡...