HC595M Datasheet PDF

CD74HC595 8ĆBIT SHIFT REGISTERS WITH 3ĆSTATE OUTPUT REGISTERS SCHS353 − JANUARY 2004 D 8-Bit Serial-In, Parallel-Out Shift D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±6-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Shift Register Has Direct Clear description/ordering information DW, E, M, NS, OR SM PACKAGE (TOP VIEW) QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8 16 VCC 15 QA 14 SER 13 OE 12 RCLK 11 SRCLK 10 SRCLR 9 QH′ Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.