LM2506 Datasheet | Texas Instruments

FEATURES - 2 RGB Display Interface Support up to 800 x 300 ½SVGA Formats - MPL-Level 0 Physical Layer using Two Data and One Clock Signal - Low Power Consumption - Pinout Mirroring Enables Straight Through Layout with Minimal vias - Level Translation between Host and Display - Auto Power Down on STOP PCLK - Link Power Down Mode Reduces Quiescent Power Under < 10 µA - 1.74V to 2.0V Core / Analog Supply Voltage Range - 1.74V to 3.0V I/O Supply Voltage Range - - 30C to 85C Operating Temperature Range SYSTEM BENEFITS - Small Interface - Low Power - Low EMI - Intrinsic Level Translation DESCRIPTION The LM2506 device adapts RGB style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. The LM2506 supports one RGB display at up to 18-bit color depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz PCLK) is supported. A mode pin configures the device as a Serializer (SER) or Deserializer (DES) so the same chip can be used on both sides of the interface. The interconnect is reduced from 22 signals to only 3 active signals with the LM2506 chipset easing flex interconnect design, size constraints and cost. The LM2506 in SER mode resides beside an application, graphics or baseband processor and translates a parallel bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near the display module. When the Power_Down (PD- ) input is asserted on the SER, the MDn and MC line drivers are powered down to save current. The DES can be controlled by a separate Power_Down input or via a signal from the SER (PDOUT- ). The LM2506 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 150 μA IB current (Class 0). Typical Application Diagram - Bridge Chips RGB Style Display Interface Apps Processor --Graphics Processor --Baseband Processor RGB[17:0] VS HS DE PCLK PD- Serializer MD0 MC MD1 Deserializer Bypass Caps. Not shown M/S- RGB- TM RM0...