LM4308 Datasheet | Texas Instruments

FEATURES - 2 18-bit i80 CPU Display Interface - Supports up to 640 x 480 VGA Formats - Differential SLVS Interface - Dual Displays Supported - WRITE and READ Operations Supported - Robust Differential Physical Layer - 400m Vpp Differential Signal Swing - Internal 100 Ω Termination Resistor - Low Power Consumption - 5-bit CRC for Data Integrity - Level Translation between Host and Display - Low Power Sleep State - 3.3V Tolerant Master Clock Input Regardless of VDDIO - Fast Start Up Time - 1k CLK Cycles - 1.6V to 2.0V Core / Analog Supply Voltage - 1.6V to 3.0V I/O Supply Voltage Range SYSTEM BENEFITS - Small Interface - Low Power - Low EMI - Intrinsic Level Translation DESCRIPTION The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level. The differential line drivers and receivers conform to the JEDEC SLVS Standard. When noise is picked up as mon-mode, it is rejected by the receivers. This is further enhanced with the 50 Ohm output impedance of the drivers. The 100 Ohm termination is integrated into the receivers. Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ operations. An Error (ERR) pin reports the occurrence of an error. A Write Only mode is also provided. The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost. A low power sleep state entered when the PD- inputs are driven low. Typical Application Diagram Memory Port (Display) 1.8V Apps Processor --Graphics Processor --Baseband Processor D[17:0] AD WR- RD- CS2- CS1- (other devices) LM4308...