Texas Instruments LM4308
The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Both WRITE and READ operations are supported. The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost.| Part No. | LM4308 |
|---|---|
| Datasheet | LM4308 Download |
| Manufacturer |  Texas Instruments |
| Description | Mobile Pixel Link Two (MPL-2) - 18-bit CPU Display Interface Master/Slave |
| Buy | Stock & Price |
FEATURES
1●2 18-bit i80 CPU Display Interface
● Supports up to 640 x 480 VGA Formats
● Differential SLVS Interface
● Dual Displays Supported
● WRITE and READ Operations Supported
● Robust Differential Physical Layer
● 400mVpp Differential Signal Swing
● Internal 100 Ω Termination Resistor
● Low Power Consumption
● 5-bit CRC for Data Integrity
● Level Translation between Host and Display
● Low Power Sleep State
● 3.3V Tolerant Master Clock Input Regardless of VDDIO
● Fast Start Up Time - 1k CLK Cycles
● 1.6V to 2.0V Core / Analog Supply Voltage
● 1.6V to 3.0V I/O Supply Voltage Range SYSTEM BENEFITS
● Small Interface
● Low Power
● Low EMI
● Intrinsic Level Translation
DESCRIPTION
Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level. The differential line drivers and receivers conform to the JEDEC SLVS Standard.
