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LMC568 - Low Power Phase-Locked Loop

General Description

The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and a carrier detect output.

LMCMOS technology is employed for high performance with low power consumption.

Key Features

  • 1.
  • 2 Demodulates ±15% Deviation FM/FSK Signals.
  • Carrier Detect Output with Hysteresis.
  • Operation to 500 kHz Input Frequency.
  • Low THD.
  • 0.5% Typ. for ±10% Deviation.
  • 2V to 9V Supply Voltage Range.
  • Low Supply Current Drain.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LMC568 www.ti.com SNAS559B – MAY 1999 – REVISED APRIL 2013 LMC568 Low Power Phase-Locked Loop Check for Samples: LMC568 FEATURES 1 •2 Demodulates ±15% Deviation FM/FSK Signals • Carrier Detect Output with Hysteresis • Operation to 500 kHz Input Frequency • Low THD—0.5% Typ. for ±10% Deviation • 2V to 9V Supply Voltage Range • Low Supply Current Drain DESCRIPTION The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and a carrier detect output. LMCMOS technology is employed for high performance with low power consumption. The VCO has a linearized control range of ±30% to allow demodulation of FM and FSK signals. Carrier detect is indicated when the PLL is locked to an input signal greater than 26 mVrms.