Description
The LMK04100 family of precision clock conditioners provides jitter cleaning, clock multiplication and distribution without the need for high-performance VCXO modules.
Features
- 1.
- 23 Cascaded PLLatinum™ PLL Architecture.
- PLL1.
- Redundant Reference Inputs.
- Loss of Signal Detection.
- Automatic and Manual Selection of Reference Clock Input.
- PLL2.
- Phase Detector Rate up to 100 MHz.
- Input Frequency-Doubler.
- Integrated VCO.
- Outputs.
- LVPECL/2VPECL, LVDS, and LVCMOS Formats.
- Support Clock Rates up to 1080 MHz.
- Five Dedicated Channel Divider Blocks.
- Common.
LMK04100 Datasheet
