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LMK61E2 - Ultra-Low Jitter Programmable Oscillator

Description

The LMK61E2 device is an ultra-low jitter PLLatinum™ programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks.

The outputs can be configured as LVPECL, LVDS, or HCSL.

Features

  • 1 Ultra-Low Noise, High Performance.
  • Jitter: 90 fs RMS Typical fOUT > 100 MHz.
  • PSRR:.
  • 70 dBc, Robust Supply Noise Immunity.
  • Flexible Output Format; User Selectable.
  • LVPECL up to 1 GHz.
  • LVDS up to 900 MHz.
  • HCSL up to 400 MHz.
  • Total Frequency Tolerance of ±50 ppm.
  • System Level Features.
  • Frequency Margining: Fine and Coarse.
  • Internal EEPROM: User Configurable Default Settings.
  • Other F.

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Datasheet preview – LMK61E2

Datasheet Details

Part number LMK61E2
Manufacturer Texas Instruments
File Size 1.33 MB
Description Ultra-Low Jitter Programmable Oscillator
Datasheet download datasheet LMK61E2 Datasheet
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Full PDF Text Transcription

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Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design LMK61E2 SNAS674B – SEPTEMBER 2015 – REVISED FEBRUARY 2017 LMK61E2 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM 1 Features •1 Ultra-Low Noise, High Performance – Jitter: 90 fs RMS Typical fOUT > 100 MHz – PSRR: –70 dBc, Robust Supply Noise Immunity • Flexible Output Format; User Selectable – LVPECL up to 1 GHz – LVDS up to 900 MHz – HCSL up to 400 MHz • Total Frequency Tolerance of ±50 ppm • System Level Features – Frequency Margining: Fine and Coarse – Internal EEPROM: User Configurable Default Settings • Other Features – Device Control: I2C – 3.
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