LMK61PD0A2 Datasheet PDF (Ultra-Low Jitter Pin Selectable Oscillator)

LMK61PD0A2 - Ultra-Low Jitter Pin Selectable Oscillator

Description

The LMK61PD0A2 is an ultra-low jitter PLLatinumTM pin selectable oscillator that generates commonly used reference clocks.

The device is preprogrammed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect).

Features

1 Ultra-low Noise, High Performance.
Jitter: 90 fs RMS typical fOUT > 100 MHz.
PSRR: -70 dBc, robust supply noise immunity.
Flexible Output Frequency and Format; User Selectable.
Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 312.5 MHz.
Formats: LVPECL, LVDS or HCSL.
Total frequency tolerance of ± 50 ppm.
Internal memory stores multiple start-up configurations, selectable through pin control.

Datasheet Details

Part number	LMK61PD0A2
Manufacturer	Texas Instruments
File Size	1.05 MB
Description	Ultra-Low Jitter Pin Selectable Oscillator
Datasheet	LMK61PD0A2 Datasheet
Additional preview pages of the LMK61PD0A2 datasheet.

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Full PDF Text Transcription

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator 1 Features •1 Ultra-low Noise, High Performance – Jitter: 90 fs RMS typical fOUT > 100 MHz – PSRR: -70 dBc, robust supply noise immunity • Flexible Output Frequency and Format; User Selectable – Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 312.5 MHz – Formats: LVPECL, LVDS or HCSL • Total frequency tolerance of ± 50 ppm • Internal memory stores multiple start-up configurations, selectable through pin control • 3.

Published: Sep 27, 2019 |