OMAP-L138
Overview
- Dual-Core SoC - 375- and 456-MHz ARM926EJ-S™ RISC MPU - 375- and 456-MHz C674x Fixed- and FloatingPoint VLIW DSP
- ARM926EJ-S Core - 32- and 16-Bit (Thumb®) Instructions - DSP Instruction Extensions - Single-Cycle MAC - ARM Jazelle® Technology - Embedded ICE-RT™ for Real-Time Debug
- ARM9™ Memory Architecture - 16KB of Instruction Cache - 16KB of Data Cache - 8KB of RAM (Vector Table) - 64KB of ROM
- C674x Instruction Set Features - Superset of the C67x+ and C64x+ ISAs - Up to 3648 MIPS and 2746 MFLOPS - Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - Compact 16-Bit Instructions
- C674x Two-Level Cache Memory Architecture - 32KB of L1P Program RAM/Cache - 32KB of L1D Data RAM/Cache - 256KB of L2 Unified Mapped RAM/Cache - Flexible RAM/Cache Partition (L1 and L2)
- Enhanced Direct Memory Access Controller 3 (EDMA3): - 2 Channel Controllers - 3 Transfer Controllers - 64 Independent DMA Channels - 16 Quick DMA Channels - Programmable Transfer Burst Size
- TMS320C674x Floating-Point VLIW DSP Core - Load-Store Architecture With Nonaligned Support - 64 General-Purpose Registers (32-Bit) - Six ALU (32- and 40-Bit) Functional Units - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point - Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle - Two Multiply Functional Units: - Mixed-Precision IEEE Floating-Point Multiply Supported up
