Texas Instruments PCI2050B
the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently. The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses.| Part No. | PCI2050B |
|---|---|
| Datasheet | PCI2050B Download |
| Manufacturer |  Texas Instruments |
| Description | PCI-to-PCI Bridge |
| Buy | Stock & Price |
FEATURES
The PCI2050B bridge supports the following features:● Two 32-bit, 66-MHz PCI buses
● 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
● Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus arbiter
● Ten secondary PCI clock outputs
● Independent read and write buffers for each direction
● Burst data transfers with pipeline architecture to maximize data throughput in both directions
● Supports write combing for enhanced data throughput
● Up to three delayed transactions in both directions
● Supports the frame-to-frame delay of only four PCI clocks from one bus to another
● Bus locking propagation
● Predictable latency per PCI Local Bus Specification
● Architecture configurable for PCI Bus Power Management Interface Specification
● CompactPCI hot-swap functionality
● Secondary bus is driven low during reset
● VGA/palette memory and I/O decoding options
● Advanced submicron...
