FEATURES
D Fully Supports PCI Local Bus Specification, Revision 2.3 D Fully Supports PCI-to-PCI Bridge Specification, Revision 1.1 D Fully Supports Advanced Configuration Power Interface (ACPI) Specification D Architecture Configurable for PCI Bus Power Management Interface Specification, Revision 1.0 and Revision 1.1 D Two 32-Bit, 66-MHz Asynchronous PCI Buses D 1.8-V Core Logic with Universal PCI Interface Compatible with 3.3-V and 5-V PCI Signaling Environments D Provides Concurrent Primary and Secondary Bus Operations D Independent Read and Write Buffers for Each Direction FEATURES
D Burst Data Transfers With Pipeline Architecture To Maximize Data Throughput In Both Directions D Up To Three Delayed Transactions For All PCI Configuration, I/O, and Memory Read Commands In Both Directions D Provides 10 Secondary PCI Bus Clock Outputs D Provides Internal Two-Tier Arbitration For Up To Nine Secondary Bus Masters D Provides External Arbitration Option D Provides CompactPCITM Hot-Swap Fun...
Texas Instruments
